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I'm making a schematic, and I'm doing it vertical style with sheet symbols, from what I understand, ports are used to go into sheets, pass connectivity vertically, and net names are used within a sheet... but when I get within a sheet with a port and I tie that port to a net name, when I compile...
I'm trying to add a prototyping/breadboard are to a pcb layout, so I've thrown in a grid of vias, now I want to link them together with traces to mimic a bread board, but I can't because they are not associated with any nets.... how can I link them together? do I have to create new nets? .... I...
I'm not sure how to access the via's in order to assign them to the net, they are part of this component's footprint. I think the rule that keeps getting violated is the electrical clearance rule, I'm just using the default rules. On my ground plane it looks like this
thanks
hello,
I have a surface mount component (8-pin soic) in altium with a thermal pad in the middle, the thermal pad in the footprint has 4 thermal vias in it. I need to connect these to my ground plane, but I'm getting several errors, and it wont connect. I'm getting Clearance Constraint Errors...
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