Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
How do i design a schematic for Counter with Reset/Pause on FPGA
Hey All!
Currently struggling a tonne getting my mind around designing basic schematics on an FPGA (Device is a Cyclone IV E EP4CE6E228). Basically the schematic is supposed to make a digit move across 3 of the 4 7-segment...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.