Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thanks for your valuable suggestions. Unfortunately, I'm supposed to continue my research in that area without any compromise with my supervisors. In this scenario, can you give me any directions? How can I move further?
Dear Mentors, I'm a newbie in this research community, and I planned to do my research in the analog ic design sizing (front end) using optimization techniques, especially deep reinforcement learning. I need all your suggestions, whether my identified research gap can have much space to explore...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
