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Recent content by oucd

  1. O

    [Moved]All digital phase locked loop books?

    Hi, I have some experience with digital pll. However, I am completely new all digital pll. I am looking for a practical design book on all digital pll. Any recommendation?
  2. O

    Assura LVS issue with IBM cmrf7sf

    VDD! and GND! are the power and ground pins. A and Z are input and output pins. The VDD! is tied to the NWELL and GND! is tied to the substrate.
  3. O

    Assura LVS issue with IBM cmrf7sf

    I used netSet to pass the global power (VDD!) and ground (GND!) of a top cell (called inherit) to a lower level cell (called INVERT_A) . VDD! and GND! were passed correctly in the schematic. When I proceeded to LVS and looked at the LVS schematic netlist and layout netlist, I realized that...
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