Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by oscarodrigo

  1. O

    Test Bench reading from an extern File on VHDL

    writing std_logic_vectors to a text file Oh! now it's working!! Thanks you so much!
  2. O

    Test Bench reading from an extern File on VHDL

    test bench reading from file mmm it doen't work if i put a readline before the read function :(
  3. O

    Test Bench reading from an extern File on VHDL

    read a file test bench std_logic_vector Hello to everyone I need to do a test bench by hand, it's necesary read from an external file that contains all the information, when I do that with modelsim, this show to me some values, but none of these values are in the external file (things like...
See more

Part and Inventory Search

Back
Top