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Recent content by orley

  1. O

    How to get any integer N prescaler or divider?

    There are 3 structures.You can refer to a doctor thesis of Design of a 2.4-GHz CMOS monolithic fractional-N frequency synthesizer.
  2. O

    Looking for an LNA design schematic

    Re: LNA design! Hello! You can refer to the radio frequency integrated circuit design by John Rogers and Calvin Plett. The cha.6 have a full discussion and method to design the LNA. Good Luck!:D
  3. O

    What is the fractional LO and the PLL?

    Re: fractional LO? This is another
  4. O

    What is the fractional LO and the PLL?

    Re: fractional LO? see it and may help you!
  5. O

    Looking for detailed topology of pipeline ADC 8bits circuit

    Re: pipeline ADC circuit see it!
  6. O

    How to increase available power gain of a LNA?

    It's tradeoff between gain and power.In RF circuits, high gain always means high power consumption.But new technology may improve the performance.
  7. O

    What is the fractional LO and the PLL?

    Re: fractional LO? Hello!VCO and Prescaler are important parts in Fractional-PLL,and sigma-delta modulator may be used in it. This a good book but you must give me your E-mail.
  8. O

    Question On test of delta-sigma F-N PLL

    There maybe two trouble with your F-N. One is your sigma-delta modulator is sometimes wrong, because its closed-loop means something wrong by my opinion. The other is your divider can't work ideally, especially in swallow counter and program counter and prescaler. Best Regards!
  9. O

    which tool to simulate PLL on transistor level??

    hspice and spectre can simulate the PLL system on transistor level ,though it is very slow but it is only a accurate method. Verilog-A only simulate PLL on behavior level and be used in simple research or verification in advance. It puzzle the IC design engineer to simulate PLL in sample and...
  10. O

    how to decrease the noise from I/O Pads in design of LNA

    Thanks for the explain of above, but could you tell me in detail?for example ,how to get best NF ? Thanks a lot !
  11. O

    how to decrease the noise from I/O Pads in design of LNA

    A problem encountered in my design of LNA. The layout have finished and post-simulation is well.But the NF is bad when I add the models of I/O Pads into the post-simulation. what can I do?How to get the ideal NF? Thanks in advance!
  12. O

    digital PFD/divider and analog VCO in PLL??

    It's not difficulty! If you put the divider bewteen the PFD nad VCO, the output of VCO is sine which will input thedivider, then you insert a circuit to make sine to square. Eg.the circuit is a OPA,and the OPA can cut the sine to square,--you may set input dc highly and load resistor(or other...
  13. O

    Question On Fractional-N PLL Test

    It means your PLL is unlocked. You try to jump some number in fraction and try it again. If your PLL always do wrong , your chip is failed. Regards! :D
  14. O

    Signal folding to the LO stage in a Folded Cascode

    Re: Folded Cascode Q of inductor is a bottleneck of RF design. You may add a buffer(Source Follow) at output. Another solution means LC tank spilt with mixer, but it's not your mean. Regard! :D
  15. O

    does anybody know any transmit line has low induct?

    You can put a paratactic inductor with the transmit line to gnd at outside of wafer. Regard!
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