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Recent content by oratie

  1. O

    SETUP and HOLD Violations on same path in same corner

    NDR (and/or shielding) is a good decision for this. Also, you can decrease driver of agressor or increase driver of victim.
  2. O

    SETUP and HOLD Violations on same path in same corner

    The simplest case: you have a huge crosstalk delta-delay. For setup analaysis delta-delay is added to net delay. For hold analysis delta-delay is deducted from net delay.
  3. O

    Chip voltage and temperature variation

    IR drop in package. IR drop in chip power/ground mesh etc
  4. O

    [SOLVED] ICC count DECAP cells

    get_cells -all -filter ...
  5. O

    [SOLVED] ICC count DECAP cells

    sizeof_collection [get_cells -filter "ref_name=~*DCAP*"]
  6. O

    Synopsys IC Compiler Verilog Parser Error

    Did you checked link_library (in addition to target library)?
  7. O

    Timing Mismatch in Cadence Genus and Innovus

    Well, in Genius you have Uncertainty:- 330 In Innovus Uncertainty 350.000 Is it 20ps difference?
  8. O

    Dynamic Power of SRAM less than Static Power

    Yes, but "Net switching power" is dynamic power dissipated by external (to sram) wireloads. While "Cell internal" is dynamic power dissipated inside sram.
  9. O

    Dynamic Power of SRAM less than Static Power

    In your example, the dynamic power (cell internal) is 88% of total power. While static (leakage) is just 10%. So dynamic is dominating.
  10. O

    [SOLVED] Total net routing length

    report_design -routing
  11. O

    Problem with Primetime link command: Unable to resolve reference

    Try this command before read_verilog set link_path "* $link_path" Just add * in your link_path
  12. O

    Tristate inverter buffer not found.

    The reasons: 1. Tristate buffer is not in your library, or it is marked as dont_use (unusable). 2. You have multidrivent net in your design, so tool need tristate buffer to implement it (is it bug in RTL?)
  13. O

    Post layout and routing Cadence innovus verification

    1. GDS vs gate-level netlist (LVS) 2. Gate-level vs RTL (LEC) 3. RTL functional simulation
  14. O

    How to include certain cells in synopsys design compiler

    set_dont_use [get_lib_cell *] true set_dont_use [get_lib_cell a b c] false
  15. O

    Relationship between tracks and delay

    Higher track -> bigger transistor (bigger gate width) -> faster transistor.
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