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Recent content by openwindows

  1. O

    I use a ftp tool test my V5-based PCIE ethernet NIC controll

    1>uni-upload or uni-download,it works well.occasionally ,the NMI error is trigered 2>if upload and download simultaneity,the NIC is halt.it cann't send and receive any packet. e.g: The upload is progress,and if start to download a big size file ,the NIC will be halt. however.if the...
  2. O

    Xilinx Virtex-5 16bit/125M PCIE PIPE Gen1 wrapper

    who have it?
  3. O

    ATCA and Advacned Switch based on PCI-express

    yes,i am interested in ASI. you are researching it? Added after 1 minutes: https://developer.intel.com/netcomms/as/collateral.htm
  4. O

    Why is the default value set for transistors in 0.09 um PDK?

    I installed the new 0.09um PDK(I used the normal install.pl command), and then copied the original design library to a new directory. But when I open the schematic and want to change the size and name of the transistors, the size of transistors were set to the default value automatically(like...
  5. O

    h.264 new standard by 2005.03

    att. btw,Anyone have H.264 codec FPGA design experience sucessful?
  6. O

    plz recommand me some USB2.0 reader card(SD/MMC) chips

    thanks! there is any USA company ic?
  7. O

    plz recommand me some USB2.0 reader card(SD/MMC) chips

    plz recommand me some USB2.0 reader card(SD/MMC) chips.
  8. O

    UMC 0.18 or 0.13um mixed-mode PDK ?

    who have TSMC 0.13um mixed-mode PDK ?
  9. O

    asyn fifo: primetime STA analysis

    sta analysis i need add the command:set_false_path for my asyn fifo 2 clocks of my design when i do primetime STA analysis in my PT script?
  10. O

    random generator verilog source code

    verilog random number generator who can post?
  11. O

    random implement verilog code

    Now,i need implement a random algorithm. The c function is R=Random[0,1]. who can help implement it with verilog?
  12. O

    how do the exponent algorithm implement in verilog?

    verilog exponent 1: (1-2^-n) 2: (1-2^-n)^6 3: (1-2^-n)^1/4
  13. O

    Who can explain the difference between clock and reset tree?

    clock tree/reset tree who can explain the difference of between clock tree and reset tree?
  14. O

    Explanation of set_multicycle_path in Verilog code

    i am a little confusion of set_multicycle_path when i synthesis my design by dc,who can help me explain it by verilog code? very thanks!
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