Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
mash simulink
Dear ALL
1.After run h-spice
.tran ts tend
.print tran v(vout+)
I get a .lis File.
Is this output file(.tran data) correct for meting digital logic correction?
2.what block can i use in matlab simulink to send the .tran output file to digital logic correction?
THANK YOU VERY MUCH~!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.