Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In contrast with conventional hard drive which are rotational mechanical devices, solid state drive uses solid state memories like NAND flashes to store data. There are different types of SDDs are available in the market but they are expensive and mostly are used in high-end servers. It is...
Dear All,
STEC Tehcnology Sdn. Bhd located in Penang Malaysia is looking for front-end engineers with more than 3 years of experience. Our company is designer / manufacturer of solid state drives. We have 5 position for ASIC engineers who have RTL coding (verilog,vhdl) experience. Candidate...
Hi All,
Can anyone know how can I get the cell type of a FF in dc_shell?
For example I have a rgister named my_design/core/dsp/counter_reg_1_1. How can I get the cell type which this FF has been mapped to?
Thanks for your help,
Hi,
I found the answer myself. so let me put it here that everyone can use. There is a command in PKS called check_nestlist. This will gives you a report on all floating net / ports , multiple driving nets and combinational loop. You can use this command so.
Regards
Hi All,
I have a question here. I appreciate if anyone can help.
How can I locate the floating net / cell in the pre/post place and route netlist?
I'm giving considerable amount of leakage current and I think one reason can be the floating nets. I'm using PKS from cadence for synthesis and...
1- Make sure all major ports like scan_mode, test_mode and specially "reset" pin have the right values.
2- Make sure, the PAD's functionality is known by tetra max and is not a black box. one solution is to define a behaviour model for PAD and import it into tetra max also.
Hope this helps
do_xform_fix_multiport_nets
Hi,
I'm using PKS from cadence as synthesis tool. In the generated netlist, there are some "assign" statements. I know how to get rid of them in synopsys' design compiler or cadenc's rtl compiler. But I don't kknow how can I get rid of "assign" statements in PKS...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
