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Recent content by oliglaser

  1. O

    Address Generator for Dual Port RAM

    Right I see what you mean, thanks. I'm going to do some more reading on how to infer the correct logic in Verilog. Trying to find some good books on the synthesis side of Verilog.
  2. O

    Address Generator for Dual Port RAM

    Thanks for clearing that up about the optimisation. I removed the always block in question and put the logic in the other always block that is sensitive to the clk edge, and it works fine. Beginning to get the hang of it a bit now.. About it not synthesising to flip flop(s) - I thought you...
  3. O

    Address Generator for Dual Port RAM

    Another thing - I am looking at the signals *after* synthesis and I notice the q signal is low when the counter is incrementing, which is opposite to the actual code (it should be incrementing when q is 1, otherwise add is 00000000) I can't figure out why this would be other than the synthesis...
  4. O

    Address Generator for Dual Port RAM

    I know there is no clock - I thought I could use it in this way... I am only starting off with Verilog so I probably don't get a lot of what is going on properly yet - all I know is it seems to work okay like this (not that I will leave it like this as I now know is not good) so the compiler...
  5. O

    Address Generator for Dual Port RAM

    Thanks for the replies and clarification. I checked the Actel HDL guide and noticed you can infer a register with three edge events - clear, preset, and clk, so maybe it has worked okay for the tools/FGPA I'm using. I got no warnings (I think) about combinational logic being inferred. In any...
  6. O

    Address Generator for Dual Port RAM

    But it did synthesise and is working.. The block is meant to start the address incrementing with the start signal (which sets st), and then it stops itself when it reaches the highest value by toggling rst. This is apparently what is happening (it simulates correctly after synthesis too), and...
  7. O

    Address Generator for Dual Port RAM

    Thanks, got the message loud and clear there :-) I will make sure I remember this - I am *trying* to follow the synchronous design method, as I read this is the best way to go for most (if not all) designs. I actually thought I had got it right with the start signal in my address generator -...
  8. O

    Address Generator for Dual Port RAM

    Thanks for the reply - I understand about the USB bottleneck, the prototype is actually built and running (at 80Msps now since my post) All the PIC is doing is relaying the data to the PC, it *may* be replaced with something like a FTxxx USB to parallel/serial IC, but the PIC is reasonably cheap...
  9. O

    Address Generator for Dual Port RAM

    Hi all, I have recently started with Verilog and FPGAs (I have plenty of experience in most other aspects of electronics though) I am prototyping a medium speed USB oscilloscope (>50Msps, hopefully up to 250Msps) using an Actel ProASIC3 150k gate device, and a PIC18F which handles the passing...
  10. O

    Libero check HDL, FlashPro Inspect Device Error

    Thanks for the reply, I discovered it does check syntax, I just couldn't see it as I had the window too small so it scrolled up and disappeared :-) With the other problem I'm not sure what you mean by read only state for the programming file. If you mean the security settings then I have set...
  11. O

    Which vendor is best for learning with..

    As regards the ADC overclocking, the ADC08200 gives 200Msps as the minimum (top) speed - in the datasheet it states that 230Msps should be attainable okay, so I figure that it may be okay at 250Msps, if not I will lower the speed. The analogue bandwidth is 500MHz so I should be okay there...
  12. O

    Which vendor is best for learning with..

    Thanks for the reply, I have progressed a bit with schematics, chip choices, board layout etc. The current plan is to go for 250Msps (for now anyway, as it's still in excess of original project goals) Also the ADC can still be got pretty cheaply at this speed, keeping prices down. The ADC I...
  13. O

    Which vendor is best for learning with..

    Thanks for the reply, I *think* Actel lets you choose too.. I'll get to that at some point as I would like to have some way of checking my HDL properly (see my other post...) I am aware about the bandwidth/frequency difference, and was planning on doing something like having the high speed...
  14. O

    Which vendor is best for learning with..

    Hi, As I mention in my other post, I have recently etched my own dev board with a ProASIC3 device to get up to speed with FPGAs (didn't fancy paying £1000 for the Actel dev board) The plan is to use an FPGA in our USB scope at >200Msps hopefully, whilst keeping prices down. Everything is going...
  15. O

    Libero check HDL, FlashPro Inspect Device Error

    Hi all, I've recently got into FPGAs with Actel. I etched my own board and am using a 60K ProASIC3. I have managed to get it working (flashing LEDs, using ABC soft core etc) okay, but there are a couple of questions I have.. 1. The check HDL feature seems to just tell you the file is either...
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