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Hi all,
Is anyone engaged in ECC implementation for storage?
I have been engaged in LDPC ECC research in three years.
All including concepts, realizations and validations are done in detail by myself.
My target is based on robust hard decoding to ensure 1KB-product stability.
Many results...
Hi,
I have some BER curves about QC-LDPC and BCH code
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I wonder what theoretical SNR gap between them is under hard decoding process.
Could anyone know about it?
Thank you.
I have implemented VLSI circuit of 1KB QC-LDPC codec in tsmc90 nm
It is (9216,8256,QC64) QC-LDPC.
This hardware costs 177K equivalent NAND gate count.
I want to know what published paper is the lowest complexity of 1KB LDPC codec.
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I find out some good LDPC codes.
There are rate=15/16 QC-LDPC codes with regular-3 variable nodes
I want to know What code design method can provide good BER performance in such ultra-high code rate.
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1KByte QC-LDPC for NAND FLASH, Deg-Var=3(variable regular)
(9152,8192,QC32) use scalar min-sum LDPC decoder with 3 bit (AWGN 8-level)
I cannot ensure error floor, but from short code it DOES NOT have error floor,
https://codebeauty.blogspot.com/2012/05/1kb-high-code-rate-qc-ldpc-for-nand.html
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