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Ok but then i assume i would have to change the order, dependent on the order i wrote the ports, so this would be correct:
bit1: FullAdder port map(X(0),Y(0),Ci,S(0),c(0));
am i right?
Thanks for the help!, i added carryin and carryout for the entity, but im not sure if i used them correctly in the behavorial. Changed code is in bold font!
Hello, im practicing on my exam to come, and im trying an old exam, i did answer two questions but im very unsure wether they are correct or not, since it was a long time since i wrote VHDL. I would appreciate if someone could check those answers and tell me if something is wrong :).
a) using...
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