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1. what do you mean by "ground"?
2. Floating metal fill can slightly increase cross-capacitance of regular nets, therefore slows them. SI and non SI results should be +- the same.
Uncertainty is a method for:
a. Increasing your ICs margins. Means you close STA timing with better margins which will outcome reliable circuit.
b. As a matter of requirement of your process manufacturer. In most cases vendors will ask you to add uncertainty and will not commit results without...
Re: LEC - why RAM as "Not Translate" or as "black box", and lib file's also in LEC.
Huge runtimes happens to me when:
1. RTL vs Netlist (full synthesis of the RTL is required).
2. Huge designs (around 300-400K of flip flops).
3. Complex design that involves many hierarchies, multipliers, adder etc.
Re: LEC - why RAM as "Not Translate" or as "black box", and lib file's also in LEC.
Well it depends on the logic complexity, but i would say on average that a basic synthesis and LEC run of 10K gates shouldn't take more than 1 hour.
Re: LEC - why RAM as "Not Translate" or as "black box", and lib file's also in LEC.
Yes, i mean a whole week.
A basic RTL vs Netlist LEC run involves actually an entire synthesis of the RTL, then mapping key points and finally comparing to the netlist.
This process can take in big blocks (over...
Re: LEC - why RAM as "Not Translate" or as "black box", and lib file's also in LEC.
Challenges of LEC:
1. Map the golden and revised design correctly and in a throughout. Make sure that nothing important is not left as not-compared.
2. When non equivalent points are found (due to synthesis...
Yes. For example, a simple inverter with X1 driving size will be implemented differently in different foundries. It will effect its timing and power characterizations.
Approximately there shouldn't be huge differences but they surely exists.
rca is right, you can go through all your AOI cells in the library and set_dont_use them.
Take into account that excluding such elementary cell from your library may cause very not-optimized design in some cases.
There are many systems and circuits to do that. You should provide more info about the pulse characterization.
You can sample the pulse line with 2 FFs in series, and compare their outputs. If the values on the signals is not equal, then you can assume a pulse was detected.
Voltage domain of a signal, For example:
A signal can be generated inside a chip (low vdd) through the chip's IO (higher vdd) and outside the chip through a PCB for instance (high voltage).
Another example can be that inside a single chip there are multiple power domain, and a signal can go...
There are many programs which you can create your wave forms after you run a testbench on your design.
After you create the waveforms on other programs you can export it as a picture to word.
Word itself is not for generating or drawing waveforms.
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