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Hi,
Intel India has intitated a Design Contest called "Intel India Embedded Challenge 2010" - an External Contest to promote innovation in the field of Embedded Technology.
Few details about the Competition: There are two categories under the competition 1) Students category 2) Professionals...
Hi,
Channel Length modulation is predominant when the channel dimensions are low. Low channel dimensions can either refer to scaled transistors or minimum length of channel.......... and this channel length modulation lambda=1/rID.....
regds
Re: About delay in MOS
Thts true...Thou increasing the width of a MOS transistor...will increase the current...but Increasing width will also increase the device capacitance which will tend to add to the delay...
vth vs width
Hi,
If you read any of the books on CMOS basics you will find explaination along with the mathematical part. CMOS VLSI Design By Weste is very good book.
OSC layout question
Hi,
For Oscillators, refer to Razavi for functionality. And Layout basics can be got from any of basic CMOS circuits. refer to P.Uyemura
find vth of nmos
Hi,
In simple terms...., A channel is a conducting path for carriers from source to drain....and as we define threshold voltage as the minimum gate voltage required to form a conduction path....and as channel decreases the gate voltage required o turn on the device...
Hi,
A layout is just a top-view. When u r drawing source and drain....u draw just a rectangle which appeared to be short...but the actual fabrication is not so simple. U first lay oxide layer followed by polysilicon gate over the wafer....and u etch out regions where u dont want...
Hi,
At saturation, FET will have nearly constant and maximum current and current merely increases with VDS. But with the influence of Channel Length modulation λ, there is influence of r0≈(1/λIsat) which will lead to a slope.
regds,
anup
Hi,
Well For good explaination of Booth Algorithm pls refer to the following:
1. https://www.cmosvlsi.com/coursematerials.html
2. CMOS VLSI Design A Circuits and Systems Perspective (3rd Edition) Neil Weste and David Harris
3. http://en.wikipedia.org/wiki/Booth's_multiplication_algorithm...
Hi,
Well Insertion delay is mainly done to achieve tolerable skew. and the tolerable skew will tell u abt the driving schemes. Driving schemes will define how ur buffers are inserted in interconnects. For this pls refer Low power Design by Yeap.
Slew: The rate of change of voltage. this in...
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