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Recent content by oAwad

  1. O

    Synth. area reduced when adding a pipeline register

    I don't think this is the case (I checked for unconnected nets). It looks like DC is trying so hard to reach the timing constraint in the first case, but results in getting an unoptimized area. When I cut the design with one level of registers, this seems to help DC find a better area. I'm not...
  2. O

    Synth. area reduced when adding a pipeline register

    I'm synthesizing a Verilog design in Design Compiler. I'm adding a relatively tight timing constraint. The reported area is quite big. When I try to break the critical path by manually adding an additional register, the area is reduced by a large factor. Any explanation?
  3. O

    Stochastic rounding for floating point

    If I want to design a stochastic rounding unit for a floating point adder in hardware (instead of a round to nearest even unit). What would be its architecture? I'm targetting to minimize the area. This is the equation of the stochastic rounding scheme:
  4. O

    Verilog shifter synthesis in Design Compiler

    variable shift
  5. O

    Verilog shifter synthesis in Design Compiler

    How is the shift ">>" operation in Verilog synthesized in Design Compiler? Does it have the same area as an equivalent barrel shifter?
  6. O

    Computer Architecture: optimizing a comparator tree followed by array of subtractors

    I'm attempting to design a circuit that takes 16 9-bit inputs, get the maximum, and then subtract each input from the maximum. Latency is not a constraint, however I'm concerned about throughput and area. Naively, I need a comparator tree of 15 comparators to get the maximum, and 16 subtractors...
  7. O

    Report detailed area in Design Compiler/ Cadence Innovus

    If I'm using Design Compiler + Cadenece Innovus to synthesis and place&route a structural design, how to report the area and percentage that each block (structure) takes from the total design area? I'd like to determine the area that each block consumes so that I optimize it first. Any info...
  8. O

    Optimize shifter synthesis in Design Compiler

    how can I create a variable that's limited to 17? yes sure, but my concern is the "shift" signal, since it controls the levels of the barrel shifter. Thanks
  9. O

    Optimize shifter synthesis in Design Compiler

    I'm using Design Compiler to synthesize a simple arithmetic right shifter in verilog out = in >>> shift "shift" is 5-bits, but I know the max. value "shift" can get is 17 so I don't need the whole 32-bit shifter. How to instruct Design Compiler to synthesize the shifter as just a 17-bit...
  10. O

    TSMC 65nm GP operating voltage

    Hi, I'd like to study the effect of varying the supply voltage on my design. I'm using DC for synthesis and Innovus for PnR. As far as I know, the supply voltage can range from 0.9V to 1.26V with 1.2V as the default voltage. First, Can I exceed the max. voltage without leakage or logic...
  11. O

    IEE 754 Floating Point addition

    Thanks for your reply. Constraining the exponent values can obviously eliminate/reduce the alignment of the summands, but do you think there is a way to reduce the width of the adder (given that one of the summands has only one bit as '1')?
  12. O

    High-Level Synthesis (HLS) vs RTL for ASIC flow

    Hi, I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level netlist, or is there a specific HLS synthesis tool? and how efficient is ASIC flow for HLS...
  13. O

    IEE 754 Floating Point addition

    As I said, one of the 2 operands is just a power of 2 (its mantissa is always zero), e.g. 1.101101x2^5 + 2^3 How can such assumption help optimize the architecture of the FP adder unit (reduce the cost of alignment, normalization, or addition)? Thanks
  14. O

    IEE 754 Floating Point addition

    IEEE 754 Floating Point addition Given that one of the two operands in an IEEE 754 single-precision FP addition has no mantissa (just a power of 2), how can this help optimize the addition operation on the hardware level?
  15. O

    interconnect scaling

    Hello all, What happens to the current in an interconnect as the interconnect gets taller ?
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