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Recent content by nyamars

  1. N

    SISO design using behaviourial modeling in verilog

    ads-ee is correct.... just check this code..... always @ (posedge clk) begin if (reset) begin out <= 0; temp <= 0; in <= 1'b1; //just for testing make it "1"... end else begin //$display(" value of in...
  2. N

    VHDL + SV in UVM in VCS

    Can anyone please tell me how to compile VHDL (DUT files) and SV files in UVM environment in VCS?
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