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Hi,
I'm simulating LDO in Spectre (Cadence). I used 2 methods in simulating the loop stability.
1. Break the loop and add an AC voltage source.
2. Use iprobe instance.
The gain plot is correct, but the phase plot is different in 2 methods. What's more, using method 1, the phase plot starts...
Hi,
I did AC noise simulation of amplifier both in open-loop and closed-loop configuration. What I found is the closed-loop amplifier noise voltage is much much smaller than open-loop one at the same frequency. How to explain this?
Hi,
I have designed a front-end readout circuit which consist of a preamplifier and pulse shaper in Mentor Graphics. Now I want a noise simulation, from transient noise simulation I got the circuit output RMS noise voltage, but how do I know each individual transistor noise contribution?
I...
When I am using BSIM4 level=60 MOS model, I read these:
NMOS: toxe=2.4948e-009
PMOS: toxe=2.5555e-009
Same technology, but gate oxide (SiO2) thickness are different, does it possible?
Than means gate oxide capacitance per unit area (Cox) are also different for NMOS n PMOS...
Hi,
I want to simulate NMOS and PMOS noise behavior in 130nm technology with Mentor Graphics tool, parameters as below:
Vds=0.7V
Id=185uA
W/L=100/0.4 um
in order to get Id=185uA, Vgs has to be set around 0.36V. I put a AC voltage signal with offset 0.36V, magnitude default is 20mV.
The...
Re: "Scientific publication" schematic drawing
Well, thank you jpanhalt and an_82. The digikey is good, but cannot change the background from box diagram to white....in that case, cannot put it in papers to publish...or can you change background?
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I found XCircuit...
Re: Analog Layout ?
Hi, Franck...
I read the conversation between you and Tarkiss, and it gave me much impression. I am a Master student, I don't have much experience in layout. Even One year ago, I don't know about the layout. When I started to learn layout, and try to do it, I was very...
Does anyone have experience in Automated Layout Generation for CMOS Op-Amp? (two-stage OTA)
What kind of Algorithm can be used for Common-centroid layout?
X_M6 OUT N$39 VDD VDD pm_hp L=0.13u W=64u M=1
So, in this case, if i want to have a transistor M6 that have the width (W=64u and M=1), can I change it to (W=16u and M=4) ?
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Thank you Keith...I simulated the op amp with (W=64u, M=1) and (W=16u, M=4), it gives the same...
Hi FvM:
Thank you for kindly replying.
I am simulating the op amp in open loop configuration. For the DC bias for my circuit I just simply implemented a DC current and for sure all CMOS in saturation region. I know AC analysis is small signal and doesn't care for magnitudes, but when I tried...
Hi,
I was simulating the conventional Op Amp (OTA) in Eldo Spice, in the AC analysis, when the amplitude of AC input signal getting higher the Op Amp open-loop gain also getting higher ( Gain and Bandwidth is increasing, Phase Margin is decreasing), why?
The open-loop gain should be...
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