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Excuse me, I meant — what was the difference between this
Does not synthesize
module Top
(
input CLK50,
output reg[5:0][6:0] HEX
);
initial begin
genvar i;
generate
for(i = 0; i < 6; i++) begin: test
HEX[i][6:0] = 7'b101_0101;
end
endgenerate
end
endmodule
and...
Thank you, comrade! It worked!
P.S. Cannot you also tell me the difference between the two designs?
Works:
module Top
(
input CLK50,
output reg[6:0] HEX[5:0]
);
integer i;
initial begin
for(i = 0; i < 6; i++)
begin
HEX[i][6:0] = 7'b101_0101;
end
end
endmodule
Fails...
I have some Verilog module with multidimensional outputs (to 7-segment LED panels of my DE1-SoC). I want to make the outputs registered. To test it, I give some dummy code to one of LED digits. Its RTL simulation passes OK, it's even compiled by Quartus, but actually it does not work.
module...
I have to use a COmpact Flash card in my FPGA project as a data storage drive. Also i have to write the data in the UDMA mode on the speed near 30 Mbytes/sec.
What solution can you advice?
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