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Recent content by NovelPanda

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    [Moved]: Can MOS transistor put close to NT_N layer??

    Thank you! Actually the spacing requirement is always fulfilled and there is no such error in DRC. My concern is that I put NT_N too closed to the core circuit and the post-layout simulation fails to capture the influences..
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    PLL using thin oxide varactor in VCO

    If the XOR PD has no cap at the output, the Vctrl always increases (though it is very slowly..) and seems no convergence reached. After I add about 2pF cap at the PD output, the Vctrl stop rising and convergence occurs. In this case, the PD will continue to generate current to LPF if the FD has...
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    [Moved]: Can MOS transistor put close to NT_N layer??

    Re: Can MOS transistor put closed to NT_N layer?? It is TSMC 40nm RF-CMOS process~
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    [Moved]: Can MOS transistor put close to NT_N layer??

    Dear all: I want to put NT_N layer between two blocks to isolate their mutual noise coupling. NT_N is an layer in which neither N or P will be doped: it is an intrinsic silicon region with high resistivity. However, if NT_N is too closed to MOS transistor, would the MOS be malfunction or...
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    PLL using thin oxide varactor in VCO

    Thanks a lot!! I added 2pF capacitor at the harmonic mixer output and the Vctrl does not show increasing at the steady-state now. If no such damping capacitor, VCTRL goes up but the frequency does not change!! Besides, I have separated the PFD into PD and FD. At the beginning FD starts to...
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    PLL using thin oxide varactor in VCO

    Thanks! I have another path for sub-harmonic injection locked to the VCO cross-coupled pair, and the normal PLL synchronized mechanism may fight with the injection locked toward their balance. Perhaps I should simulate longer to observer if they can reach at a steady state?
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    PLL using thin oxide varactor in VCO

    Dear All: I am designing a conventional integer-N PLL in 40nm CMOS. In LC-VCO part the varactor is implemented by the thin oxide accumulated-mode MOS. When the PLL toward locked, the average current of charge pump output is nearly zero (nA level). However, I observe that the control line...
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    Evaluation of PLL noise by transient

    Dear All: I realize that it is difficult, or impossible, to get a explicit result of PLL phase noise through Spectre transient simulation, but we all note that the rms-jitter is the integration of PLL phase noise from DC to infinity. Most probably the way we did to evaluate the PN of PLL is...
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    PEX after dummy fill

    Thanks! But what I found is that the dummy should be physically floating but "short" to ground during C+CC extraction? How come a 54um*54um Pad can have over 300fF capacitance with respect to the ground?
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    PEX after dummy fill

    Dear All: I am now running PEX after dummy fill and evaluate its impact. I use TSMC 40nm RF process with automatic dummy fill script provided by foundry. During the test of VCO, I use dummy blocker to enclose the varactor and interconnects, leaving other space automatically filled by dummy (the...
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    Resonance found between probe (finite inuctance) and circuit

    Resonance found between probe (finite inductance) and circuit Dear All: I have designed a 30GHz PLL which I plan to use probe for testing. There are approximated 100pF equivalent cap between VDD and VSS inside the chip after C+CC extraction. The probe is estimated to have about 20pH inductance...
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    Long interconnect between digital and analog blocks

    Re: Long interconnect between digital and analog blcoks Thanks freebird, quite useful! I am routing only some control bits that have no RF or timing issue with regard to those 1mm long interconnects..
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    Long interconnect between digital and analog blocks

    Long interconnect between digital and analog blcoks Dear All: Due to chip planning reason, I have separated the digital blocks and analog ones far away from each other. However, the digital control line must travel a quite long distance (~1mm) before they reach the analog parts. Such...
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    Can Use Top Al layer to transmit High Speed data?

    Dear All: I have an small circuit that has intensive interconnections which may suffer from noticeable crosstalk. To alleviate this I may resort to using the top aluminium (M11) to transmit high speed data (>30Gb/s). However I did not use this metal layer before except for PAD. In addition to...
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    Interesting Problem with on-chip PRBS Design

    Dear All: Due to limitation on measurement facilities, I need to design an on-chip 28Gb/s PRBS to generate data stream for testing. To minimize area and achieve high speed, I have designed a full-rate PRBS-4 which is composed of 4-DFF, 1-XOR and 1 additional DFF for re-timing. The DFF is...
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