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Recent content by noloser

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    Xilinx Virtex-4 ML403 16x2 LCD

    vhdl code lcd 16x2 Thanks echo47. That is what i wanted. By the way, I am curious about where you find the coding and the location for the pins connected to the LCD. Because what i found in the data sheet of ML403, i only saw that the pins are connected to the GPIO and never mentioned about...
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    Xilinx Virtex-4 ML403 16x2 LCD

    xilinx lcd Hi Iouri, Thanks for the help. I know the initilzation for the LCD. The LCD is embedded on the development board, ML403 and from the data sheet, it is connected to GPIO, which i don't know hw to access these I/Os. Some of the on board LEDs have pins assigned to them so i know how...
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    Xilinx Virtex-4 ML403 16x2 LCD

    ml403 datasheet Hi all, I am a student. I am new to verilog and FPGA. I have a question. How do I use the 16x2 LCD which is on the development board? I have a verilog code which I want the LCD to load the ASCII char from the verilog code I written. The verilog code is just a few shift...
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    C++ programming based on MFC on file saving?

    Thank for all your info, it's really helpful.
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    C++ programming based on MFC on file saving?

    anyone can provide some useful links to sample C++ source that demostrate saving of file using MFC libraries. i am currently using visual studio .net 2005 to do the compiling. any useful books or articles are greatly welcome, thank in advance!!
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    Regarding UART modeling through FPGA.

    which mean i will design the code such as logic '1' is high voltage and logic '0' is zero voltage and after completing, before using it, i need to design another driver circuit using the MAX232 chip, am i right? Thank for your info!
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    Regarding UART modeling through FPGA.

    does that mean when a design a UART interface on FPGA to communicate with the serial port on a desktop computer, i can just treat logic '1' as high voltage and logic '0' as negative (or zero) voltage level? any link to spec sheets or articles to show these info? thank alot!!
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    Regarding UART modeling through FPGA.

    I am modeling a UART interface using FPGA through VHDL, but there are some spec which i got confused. is the UART chipset found in most desktop PC decode a negative voltage as logic '1' or a positive voltage as logic '1'? I read some articles on RS232 communication, some saying one way while...
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    Question regarding delaying signal with FPGA in VHDL?

    Thank for your info, at least i won't waste time write a code that end up not working in the hardware. can time constraint be different for different module within a single project?
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    FSM - finite state machine

    is it die die must be model in FSM? this shall be much easier if you model in behaviour mode. just capture the serial input, convert it to integer and check for the value mod 5 equal to 0 will do the work.
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    Problem with "kuft" command in VHDL

    vhdl problem. why not use FSM model for it. it would be less confusing in that case, isn't it? just test for the require inputs then decide the next state to go, and create the desired output within that sate without using complicated calculation as output for every state are normally fixed in...
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    frequency generator in VHDL

    frequency can be easily divided in a multiple of 2T timing by using counter in behaviour structure. for any other frequency value, other frequency value, you need to use PLL method which shall be an analog method which are normally support by the chip company through their own build-in macro. as...
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    Question regarding delaying signal with FPGA in VHDL?

    is the "after" operation of VHDL synthesisable into a actual hardware design or it was only be used for simulation modeling? let say, if i write: a <= b or c after 20ns; will the synthesised hardware actually update the output after (appx) 20ns after a change in inputs or it will just use the...
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    Explanation of relativity with examples

    what is relativity? Weird! According to relativity, no motion in this world shall exceed the speed of light, so v >> c is impossible! Added after 18 minutes: Well, as far as i know, for both general & special relativity, it state that time is not a constant as everyone in this world used...
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    Initial is not synthesizable.. why?..

    Does that mean i am allow to capture a input in form of logic-vector, convert them into integar variable/signal, then do some arith operation with the value and return the result as the upper limit of a for loop. Is this structure synthesizable on FPGA chip? Sorry, i only know how to write in...
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