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Recent content by nohj_yar

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    Full CHip netlist in COnformal

    Hi all, I'm doing a FEV on RTL vs full-chip netlist, but the problem is during modelling the revised(full chip) design, it is stuck at 96%.. What are the practical reasons for this? THanks for your help..
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    Using seq_constant in Conformal

    Hi all! I'm running formal equivalence on RTL to Gate-level netlist. One of the errors that i encountered is the reset DFF's of revised is connected directly to ground and in the golden the reset is connected to the GSR. However, when i used the option set flatten model -seq constant, the...
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    Add renaming rule in COnformal

    Hi all, I used this command add renaming rule r6 "uio_tbank[12]" "bcode_led" -map -type PO -revised, but it is not working. How to remedy this? THanks a Lot..
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    Add instance constraints command

    yeah... i already tried that. also, i've tried invoking this commands: add instance constraints 0 fab_reg -module sram_bin_bit_jet -replace -revised add instance constraints 1 /b_l_blck/rap/row_9_/mim_4_/i1/II/fab_reg -replace -revised add instance constraints 1...
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    Add instance constraints command

    but in my design, i have multiple module sram_bin_bit_jet that have fab_reg, will it not affect other fab_reg in other module of sram_bin_bit_jet?
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    Add instance constraints command

    Hi all! I am using this command: add instance constraints 0 fab_reg -module sram_bin_bit_jet -replace -revised fab_reg is a register in module sram_bin_bit_jet.. Does this mean that ALL fab_reg register in module sram_bin_bit_jet in my entire design will be constrained to 0? THanks..:)
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    Floating SIgnals REport: Undriven and Unused

    Hi all! in the conformal LEC, report floating signals command, what's the difference between these two categories? Undriven floating signals and unused floating signals? Hope there will be some illustrations. However, explanation will do.. Thanks so much in advance.. JR
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    Using add net attribute : COnformal tool

    Hi all.. I tried to use the add net attribute command in the conformal and force the net to be in VDD or GND. If i force the it GND, the matching will definitely not pass, however if its VDD, its passing. this is the command that i used: add net attribute VDD n20[0] -golden or...
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    Using Net COnstraint : COnformal tool

    Hi all! I used the add net constraint in my rtl design. However, the conformal tool still has a passing result even i constrained the LSB(counter_c[0]) of my counter. add net constraints one_hot counter_c[0] -golden report net constraint Why is this?? Thanks..
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    [CONFORMAL] COnformal Ultra LVR (final SPICE netlist)

    Hi all! Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final...
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    COnformal Ultra LVR (final SPICE netlist)

    Hi all! Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final...
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    Verilog: Using force comman in the DUT..

    HI all! I understand that the force command is not supported by synthesis. Is there any way to write it in the DUT? Or is there a way to force a signal (without using the force command) inside the DUT without writing it in the testbench instead write it inside the DUT? THanks...
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    $setuphold syntax, verilog..

    Hello everyone.. I have some trouble of understanding the syntax $setuphold (reference_event, data_event, setup_limit, hold_limit);. I've encountered a code that looks like this $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); What i don't understand is the part, "...
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    unmatched key points in conformal

    Hi all.. THese are the few lines that i extracted in the logfile using conformal. And i have a few questions. // (F30) Ignored 3 weak device(s) due to the existence of strong device(s) // Warning: Golden and Revised have different numbers of key points: // Golden key points = 14 // Revised key...
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    [SOLVED] Conformal Tool in FPGA Full CHip design

    Yeah you are right @sharath666. I'm not replacing the verification through simulation, i'm just want to prove in my study that formal verification between full chip fpga netlist and gate level netlist is feasible..:)
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