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no0ona

Recent content by no0ona

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Frequency devider verilog code (50mhz to 75 micro second)

oh Thanks. But in my diagram the input is 50miliHerts and the output is 75micro second, so I think in the beginning I should change the frequency to time so it will be 20second. And my question is how I can write the code in Verilog for the same diagram??
- no0ona
- Post #5
- Oct 22, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Frequency devider verilog code (50mhz to 75 micro second)

I didn't get what you means, can you explain your question
- no0ona
- Post #3
- Oct 22, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Frequency devider verilog code (50mhz to 75 micro second)

Hi, I have a divider have an input of 50mhz and the output is 75micro second. How I write the code for this divider in a Verilog?
- no0ona
- Thread
- Oct 22, 2014
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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