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Recent content by nizdom

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    Inequality operator in VHDL

    Hi guys. I've read that the inequality operator /= can be used inside an IF statement. My scenario is if let's say ASSIGNMENT is an Integer array of 4 from 0 to 3, and if none in the array has a value of 0 let's say ASSIGNMENT = [2 3 1 1], then I would assign a certain signal a bit vector value...
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    Trigger Signal in VHDL

    If I implement the code, TSS_TRIGGER is just the same with TSS_DONE during the clock cycle. TSS_DONE gets high only for one clock cycle and then goes back to zero. What I want to happen is when TSS_DONE gets high for a clock cycle, on the next clock cycle, a signal will get high for that clock...
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    Trigger Signal in VHDL

    Hello guys! I think this is a basic question but I hope you can help me. For example, I have a signal DONE that will be high for a certain time for 1 clock cycle. How can I create a signal that is same with DONE and will occur exactly after DONE and also 1 clock cycle. Thank you.
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    Pipeline problem VHDL

    Oh I didn't see it! Thaaanks!
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    Pipeline problem VHDL

    What kind of flip flop should I use? Thaanks!
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    Pipeline problem VHDL

    Hi guys! I need some help. Here is the scenario, in the first timeslot (or one cycle), a value is outputted. Then on the next timeslot, the same signal but it is already updated to anew value. What should I do so that I can use the value from the first timeslot during the second timeslot. Take...
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    matrix array from instantiations

    I just need to assign them to a larger array but they have the same signal name. is there a way I can assign them a different name?
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    matrix array from instantiations

    But they have to be picked up at the same time and assigned in an array at the same time. Isn't it possible?
  9. N

    matrix array from instantiations

    What if I have 2 instantiations then both has PORT_ASSIGNMENT which is an array of integer and I want to use these two sets of arrays? How can I do that? Like I have PORT_ASSIGNMENT from Instantiation 1 then I have another PORT_ASSIGNMENT from Instantiation 2. Then I want to place these values...
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    Matrix array inside a for loop VHDL

    Now I am having an internal error. Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/vrfx_verific_elaborator.cpp, Line: 2144 c Stack Trace: 0x61d46: VRFX_ELABORATOR::elaborate + 0x8566 0x61c87: VRFX_ELABORATOR::elaborate + 0x84a7 0x61167: VRFX_ELABORATOR::elaborate +...
  11. N

    Matrix array inside a for loop VHDL

    I have already included the CARDMATRIX_TYPE in the package. Now the error says CARD_MATRIXA does not agree with its usage as CARDMATRIX_TYYPE. Can someone help me find out why? Like I have checked it already but I still don't know why. Code is below. PORT_SIZE = 4 in this code. LIBRARY IEEE...
  12. N

    Matrix array inside a for loop VHDL

    Error says "object "CARD_MATRIX" is used but not declared"
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    Matrix array inside a for loop VHDL

    So how can I make the matrix array assigned to CARD_MATRIX as an output in the port declaration? Any idea?
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    Matrix array inside a for loop VHDL

    This is the entity block I am working on. This is only one of the entity blocks I am working on. I am having problems with declaring CARD_MATRIXB as an output in the PORT Declarations. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; USE...
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    Matrix array inside a for loop VHDL

    What would be my type declaration for CARD_MATRIX if I wanted to make it as an output in my port declaration? would it be integer? TYPE CARD_MATRIX IS ARRAY (0 TO PORT_SIZE-1, 0 TO 7) OF INTEGER RANGE 0 TO 256; SIGNAL CARD_MATRIXA : CARD_MATRIX;
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