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Recent content by nitu

  1. N

    Software engineer in chip company ?

    Hi Chethan, Thanks for the reply. It means that Software engineers referred by the chip industry are the engineers who understand the scripting language for EDA tools. Is this correct ?
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    Software engineer in chip company ?

    Hi.. I have been to conference recently and met people working on ASICs. All of them shared that ASIC development team now has large number of software engineers(approx 50%). I not sure why will they need so many software engineers. Is it for embedded software development or application...
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    converting x input to x^3

    Hi.. May be two multipliers in series would do the job.. k = a1*x*x .... output of multiplier one m = a1*k * x ... output of multiplier two Hope this helps you..
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    Please, any ideas about for FFT with 6 bits OFDM receiver.

    Re: Please, any ideas about for FFT with 6 bits OFDM receive Hi.. The problem is not clear. Are you asking how can we have FFT at TX side is generating output of 16 bits and IFFT at RX which can take input of 6 bit ? Or how to code FFT/IFFT which can take 6 bit input and generate 16 bit output ?
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    What does IIP3 +5dbm mean ?

    Hi.. Answer 1 Yes, you can infer IIP3 from P1dB and vice-versa. The relation mentioned in (1) is valid when there is no external interference present and true for linear circuits like amplifier. P1dB is input power level at which the output power is 1dB less when compared to idle case ( Output...
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    verilog code to generate random sequence

    Hi.. You can find it link below. You need to register to get it. https://www.opencores.org/project,systemc_rng Hopes this help..
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    RFIC which can support bandwidth from 2-11 GHz

    RFIC required: 2-11 GHz Hi .. I am looking for RFIC which can support bandwidth from 2-11 GHz. It can be single chip or multi chip. Please let me know if you have one or know who may have this one. Thanks for your time.. Nitu
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    Channel Capacity calculations for Modulation techniques

    Hi, The document attached gives the formulas for channel capacity for modulations scheme. Hope this helps.
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    How to view synthesis results in Xilins ISE

    ise view ngc Hi.. In ISE 9.2 you can see the utilization of LUTs and slices in the Synthesis report. I am not sure whether the same is there in ISE 10.1. Also, you need to change the properties of synthesis after right clicking on the synthesis in the process window. Now with different...
  10. N

    Decide between PLL, DLL and FLL

    Hi.. The application targeted is an Digital block used for modulating and demodulating signal. The maximum frequency targeted is 200-250MHz. There are 2 different clocks running in the system.
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    Decide between PLL, DLL and FLL

    pll fll dll Hi.. I want to know how does an System designer finds whether his/her design needs a Phase Lock Loop, Delay Lock Loop or Frequency Lock Loop. On what information does Designer takes the decision ? Thanks.. Nitu
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    Resource usage for IP

    Hi.. I am working on a Digital IP. This IP is right now tested on FPGA. As next step, I need to find resource estimation it is going to take 0.18u CMOS technology. I will like to know whether there is a way to map resource usage in FPGA to IC. Xilinx FPGAs is been used and has resource data...
  13. N

    Correct IO Standard for 125MHz signal..

    differential signal buffer for spartan 3a Hi.. Thanks again.. I am not been able to locate the IO standard LVDCI in Spartan 3 and 3A. Please help me in locating this..
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    Correct IO Standard for 125MHz signal..

    how to specify iostandard in ucf file spartan 3 Hi Mta97e, Thanks a lot for your reply. I will like to know whether non-differential standard LVTTL can also work ? Also, is there data on maximum possible signal frequency supported by different IO standards. Thanks..
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    Correct IO Standard for 125MHz signal..

    lvdci Hi... I am designing high speed transceiver on PCB, which has ADC signals which are interfaced to Spartan 3A FPGA at Bank 3 by LVPECL standard. This interface works at 250MHz. Signals from the Bank 1 of this Spartan 3A FPGA are interfaced to I/O of Spartan 3 FPGA. These signals works at...
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