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Recent content by nishi123

  1. N

    creating verilog netlist from schematic

    How can i generate verilog netlist from schematic using Virtuoso 6.1.6?
  2. N

    Gate Ensemble and Silicon Ensemble

    What is the difference between Gate Ensemble and Silicon Ensemble?
  3. N

    target and link library

    I am learning to use dc_shell for synthesizing Currently I am trying to understand why I have to set a link_library and what is the difference between link_library and target_library. To understand what the tool does when I set a link_library, I synthesized the same design twice. First without...
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