Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi
I have designed a sequential cell that computes a logic function. I want to use this cell as combinational cell because both its clock and data are generated independently (there is no global clock). Therefore I am using data-to-data setup check in RTL compiler.
I am able to let the tool...
Hello,
I have a mapped netlist with multiple flipflops driving a single net (that I got from somewhere). I want to re-synthesize this mapped netlist using RTL compiler. But I want RTL compiler to eliminate multiple drivers and have a single flipflop driving each net. But I want RTL compiler to...
When performing Monte Carlo using HSPICE, does the order in which transistor devices are listed in the netlist, matter?
I am working with certain 90nm design kit where changing the ordering of transistor instances is showing different results. But if that's true,
is it a fault/feature of HSPICE...
The problem could be with the large units used by report_block_powr. The leakage is pretty small number and may be rounded to 0 when higher units are used. Try changing units using
set_sim_ires=1pA
set_print_ires=1pA
in the cfg file.
I think what might solve your problem with most certainty is...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
