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Recent content by niklar

  1. N

    How can I generate my own .IOC file?

    AreaPdp and IOC file In any tutorial I find on AreaPdp they always specify an .IOC file, already generated. How could I generate my own .IOC file?
  2. N

    VHDL to C/C++ converter needed

    VHDL to C/C++ converter? Could anyone give me a link to a good (and maybe free?) VHDL to C/C++ converter. Thanks.
  3. N

    Toplevel Verilog with VHDL entities

    Well, we are trying to run Design Analyzer of Synopsis. There is a relativly good tutorial on Verilog design. However, the code we have is written in VHDL. Thus, we either have to "force" Design Analyzer deal with it or make a toplevel verilog code and somehow instatiate VHDL entities in it...
  4. N

    Toplevel Verilog with VHDL entities

    Hello, I have several VHDL entities that I would like to instantiate in a toplevel Verilog file. How can this be done? Thanks
  5. N

    Any material on Codes for Testing & Fault Tolerant Compu

    Hello! I am trying to find a hottest subject in this area. Any body has any ideas on that? Thanks.
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