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as we konw, the bandgap is very important to many analog circuit. If we find the output of a bandgap after tape out differ largely from the output that we get through simulation, what are the main or the most possible reasons? what can we do to get a steady output from this bad bandgap in chip...
hi, everybody, I'm doing a post-layout simulation using the lpe hspice netlist and two troubles puzzled me now. I hope somebody can help me.
*the first puzzle: as we all know, the foundry usually has a limition of "w" value about the mosfet, so when we design a big mosfet, we used a legal "w"...
Re: why only "vdd" can be recognized as powernode
what place do you mean put "!" in? lvs command file or layout? cdl netlist used "vda!"as default. I have used the "vda!" in lvs command file and layout at the same time, but the result is almost the same: no power is found.
thank you all the...
hi, everybody, would you help me?
When I run LVS using Dracula(REV. 4.9.05-2002), I found only "vdd" can be recognized as power-node. If I changed "vdd" to
"vda" or "vddd" in both the CDL netlist and layout gds2, the *.lvs showed the message as follows:
*/W* WARNING: NO POWER ON SCHEMATIC...
thanks for all your help. now I have used "FILTER-LAY-OPT " to eliminate the errors successfully.
at the same time, I think the suggestion of "insert all your dummy in schematic" is very good but needs more time , I will use this method in the future.
Added after 19 minutes:
another question...
when I finished my LVS and see *.lvs report file, I found the dummy transistors usually causes some errors, and reports show the layout and schematic unmatched. I know these errors were not important, but affirming these errors also took me a lot of time. are there any good methods to deal with...
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