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Recent content by nicoxp31

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    [FPGA Xilinx Virtex5] Clock Multiplexing "glitch-free&a

    virtex 5 bufgmux Hi, No, the thing is that i'm not instanciating any of these BUFGCTRLs...the PAR tool may replace some other Xilinx standard modules by this BUFGCTRL automatically..because I am only instanciating either BUFGMUX_CTRL, BUFGMUX or BUFG in my verilog files. Well, I will try with...
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    [FPGA Xilinx Virtex5] Clock Multiplexing "glitch-free&a

    bufgmux virtex 5 Hi, Are you using SynplifyPro for synthesis ? i am using it. But there is a Warning in the synthesis reprot indicating that the BUFGMUX_CTRL : @W: MT246 |Blackbox BUFGMUX_CTRL is missing a user supplied timing model. This may have a negative effect on timing analysis and...
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    [FPGA Xilinx Virtex5] Clock Multiplexing "glitch-free&a

    bufgctrl Hi, I'm currently using a Xilinx dedicated-virtex5 primitive module for a clock multiplexing function called "BUFGMUX_CTRL". During synthesis I faced several problems with this module which gave some bad performance in terms of clock timing. This module is considered as a...
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    [FPGA] Clk Multiplexing

    Sorry but i do not understand how your schematic can improve the clock multiplexing since we are still using logic behind !
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    [FPGA] Clk Multiplexing

    fpgaclk Hi, I just wanted to know if they were any danger about multiplexed clock in a FPGA design: for instance: assign clk_o = tx_sel ? tx_clk_i : rx_clk_i; Can this generate instability then? Thanks, Regards, Jerome
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    [FPGA xilinx] UCF/NCF constraint files ?

    fpga ucf Hi, I have a NCF constraint file generated after synthesis (using synplify pro) and after this, i am using the Xilinx ISE design flow (NgdBuild, Map & PAR) to finally get the netlist to put on the FPGA. The problem is that the ISE flow is requesting a UCF File that I need to write...
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    [FPGA] Synthesis using Synplify - HowTo disable retiming?

    fixgeneratedclocks Hi, I have some problems using Synplify Pro v8.8 for my FPGA design flow. It seems that the tool enables retiming and pipelining register where as I ordered from the project file a disable of any retiming using the following set_options command: #device options set_option...
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    [FPGA] How to reduce Hold errors ?

    hold errors The synthesis tool (synplify) recognized the clock signal since it created a clock buffer but i am not sure that the place-route tool detected it. In the UCF file which is the "link" between synthesis and place-route tools (ISE tool) timing constraints, should I insert a special...
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    [FPGA] How to reduce Hold errors ?

    hold violation fpga Hi, After having used the traditional design flow on Xilinx ISE tool (FPGA Virtex-5), i have still some hold timing violations. Here is one example: Timing constraint: TS_XXXXX = PERIOD TIMEGRP "XXXXX" 166 ns HIGH 50%; 167 items analyzed, 15 timing errors detected. (0...
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    [Methodology] - How to solve setup timing errors ?

    Yeah this is an IP core, so no pipeline is allowed this time. however, when we take a look to the data path given above, the clock signal is going out from 80c51 and going into one of my external module, so on and so forth ... So a first idea should be to put these 2 modules closer at each...
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    [Methodology] - How to solve setup timing errors ?

    Hi, thks for yr answer. I tried different options during mapping and PAR. I noticed that the following options improved quiet a lot my design timing report: -timing -xe n However i have still some timing errors but less than before... If you have some others ideas about how to improve it...
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    [Methodology] - How to solve setup timing errors ?

    Hello, I need some help concerning some setup timing violations occuring in my design with a negative clock skew. my hardware is xilinx virtex-5 and i am using xilinx ise tool (TRACE) to get timing analysis. I would like to know what is the general methodology (any advices) when this kind of...
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