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I have a question regarding the DDR SSTL termination.
The JEDEC Standard (JESD8-9B) about the SSTL Interface for DDRs shows two possible termination methods, class I with single parallel termination and class II with double parallel termination, Figures 4 and 5 of the Standard respectively...
Well, after some days the answer came to me: I had used a wrong value of the series AC-blocking capacitors. Specifications say min. 75nF and I had 10nF on the direction endpoint -> root complex. I changed them and everything was ok after that...!
Hi,
In a system of ours, we have a CPU that is connected over PCIe with an on-board FPGA.
CPU is root complex, compliant with 2.0 and 1.0 and the FPGA is the endpoint (only 1.0 compliant).
Unfortunately the CPU tells me that the link is down (it's a new design, I have never seen it come up...
Well, I should say the answers of asdf44 and Dan helped a lot in understanding the situation. And it is of course obvious that there is no relationship with the Ethernet design, that's true. Now I think I can apply a similar concept to my design as well.
There is sth I would like to clarify...
Hi guys,
Does anyone have experience in selecting fans for cooling electronic systems?
I have read several online guides from the various manufacturers but there is something that remains unclear to me. They all have this formula where you can calculate the minimum required air flow created by...
Thanks for your reply David. I already have some knowledge about placing such capacitors between power supplies and ground, but the thing is that here there are also caps between the different power supplies. I suppose their purpose is sth similar?
Hi everyone!
In the schematics of a reference design of an Ethernet Switch with 10G Interfaces, I have seen that the designer has used several capacitors that he called "Return Path Capacitors". These are 100nF and placed between the power supplies (see attachment). Some also placed towards...
Hi guys,
although I have read lately several books and papers about ΣΔ ADCs, I still have not managed to get a clear answer to the question: Why do those ADCs have idle tones for DC or low amplitude tone inputs? Could someone explain me the mechanism behind this problem?
Moreover, as far as I...
Yes, I think that this is it. I checked more carefully my CRC and it was not correct, so I guess this must have been the problem. Now it remains to correct the error and re-do the test. It would be interesting to know in the end if the switch dropped those packets with bad CRC. thanks for the tip!
Should I? And what if the CRC I'm transmitting is wrong? Then when would the frame be rejected?
I'm actually seeing all the in/out traffic through the card. So I guess if I received something I would have seen it.
I'm not sure about that, but isn't it true? If there is incoming traffic...
Hi!
I have created a MAC transmitter in a Xilinx Spartan-6 FPGA that is externally connected to a PHY Marvell 88E1111 IC. On the FPGA development board (SP605) there LED indicators for the Ethernet. I have now connected my board with a Zyxel switch (that supports Gigabit ethernet) and from...
Hi to everyone!
I am currently implementing a Gigabit Ethernet Controller and I am quite confused about the order that the data are transmitted, how to compute the CRC and how to transmit it. So, I will give an example so that we have something concrete to talk with.
Suppose that we want to...
Hi!
I have implemented the Riordan's circuit and chosen the impedances in such a way so as to create a large equivalent capacitance with a value that is controlled by the value of a trimmer. It is actually a capacitance multiplier. I intend to use this circuit in an LC network in order to be...
To be honest, I have never thought of this possibility. I always had in mind that if I want to run the ADC slower, then the clock is what I should change. However, there is no indication in the datasheet that reducing the clock frequency would be better at lower conversion speeds; not at all. So...
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