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Recent content by nibo_mmx

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    a basic question about PDK(Process Desgin Kits)

    Dear all, as a beginner, I want to ask What PDK (Process Desgin Kits) excactly includes? include drc, lvs files from foundry? any other things? Thanks a lot
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    what's the commond of changing a file's name?

    Sorry for asking this stupid question. I just forgot the command and this no referance on my hand. thanks. waiting online
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    Question on GM from Razavis book

    Re: a basic question on gm Thank you very much. My foundation is really poor, but I try to make clear everthing I don't understand. Thanks
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    Question on GM from Razavis book

    Re: a basic question on gm Okay, I understand what small signal means in the equation. But based on the above discussion, I cannot understand the following statement in Razavi's book. I draw the figure as below: in Razavi's book (P122), he wrote: Since Id1 and Id2 stand for the small...
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    Question on GM from Razavis book

    Re: a basic question on gm Thanks a lot for your reply. Can I understand your explanation in this way: you said: so does the small signal current Id1 mean a small variant current on the biasing current Id. We can wirte it as ΔId? Say, if the biasing Vgs is 1V and the basing current is 1mA...
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    Question on GM from Razavis book

    a basic question on gm When I am reading Razavi's book "Design of Analog CMOS IC" I saw: Id1=gm1*Vgs1, I don't understand why. Because, gm=µ*Cox*W/L*(Vgs-Vth) and, Id=1/2*µ*Cox*W/L*(Vgs-Vth)² Then, How could Id1=gm1*Vgs1? I am really confused. I know I must confused some fundmental...
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    how to simulate SNR of DAC in the candence

    I heard on said DFT could only see the distortion, SNR is related to noise analysis and should use something related to ac analysis. But I dont know how
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    how to simulate SNR of DAC in the candence

    bad_egg3: Could you please give us more details about it. What's spw and how to set up it?
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    How challenging is it to design a PLL with 50ps Jitter and 100MHz clock output?

    Re: PLL Design Hey amarnath, I am interested in how to calculate p2p or rms jitter by the eye-diagram plot? Could you give us more details about it. I am also working on the design of PLL, but wonder how to calculate the jitter. Thanks in advance
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    a basic question about cascode amplifer

    Thank you all, I understand it now.
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    a basic question about cascode amplifer

    Dear ambreesh, Thanks for your post. Your disscusion make the question clearer and clearer. As I asked in the former post: How would it work if Vx initiallly is higher than Vb-Vth2, say V1? In that state, M2 and M1 are all off, and the charge at the capacitor has no way to follow, so Vx will...
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    a basic question about cascode amplifer

    VVV, Thank you very much, I understand your explanation now. Do you agree with ambreesh's point? James
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    a basic question about cascode amplifer

    Dear ambreesh, many thanks for your idea, but I still have a question. In your post: "You have a capacitor at node X and this gets charged" You mean when the capacitor is charged to Vb-Vth2, then M2 is off and there is no current to charge the capacitor anymore, so Vx will approximately...
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    a basic question about cascode amplifer

    I can undersand why Vx cannot be smaller than Vb-Vth2. But I am not sure I can fully undersand why Vx cannot be greater than Vb-Vth2. The following is my undersanding. Could you please see if I am correct? Thank you in advance: When Vx is greater than Vb-Vth2. M2 truns off and the sum...
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    a basic question about cascode amplifer

    The book says Vx≈Vb-Vth2. Since Vx≤Vb-Vth2 Then why Vx cannot equal to a value much smaller than Vb-Vth2, such as 0 or 0.1mV? Why should be approximatly Vb-Vth2?(i.e. why must be at the edge of "on"?) Thanks James

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