Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
error amplifier
Dear Forumites,
Has anybody implemented error amplifier for compensation of regulator using Verilog-A. If so can anyone post the verilog-A code which can be used for type-2 compensation. I have tried creating one using model writer, but to the failure. So looking forward for...
Hi LvW,
Yes i have tried keeping high gain around 80db, offset as 0 and even tried reducing rin, but no luck. I am posting my schematic so that you can help me fix it further.
Ni1009
Dear LvW,
please find the verilog-A code which i have been using. i have set a gain of 32db and pole freq of 0 for opamp.
********************************************************************
// FUNCTION: Ideal/Non-ideal OpAmp
//
// GENERATED BY: Cadence Modelwriter 2.30
//
//...
Dear LvW,
thank you for the reply. Infact i have reclaculated making sure about C1, C2 terms in the equation and found the same waveforms for new set of values. Let me tell you that i am using a non-ideal opamp model (Verilog-A) created using model writer and have set some gain(43) and pole...
Dear friends ,
can some one share some details about type-3 compensation simulation for DC-DC development. I have simulated type-3 given in intersil document which i have attached. But whatever i have simulated is bit revese and stange also. So please can some one eloborate/help on this.
Ni
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
