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Ic, so let the sampling frequency is 48kHz and up sample 128 time to 6.144MHz. My desire signal bandwidth is 20kHz. After nomalize where 1=fs=6.144Mhz. My desire signal bandwidth will be at 20k/6.155M = 0.003. So from the graph given, the sigma delta modulator can supress the noise up to -120 db...
Sorry, i still not get it. May i know what information can i get from this graph. For example the graph increaser from -120db to around -40db when the sampling frequency increase, what message it bring? higher frequncy will get lower noise rejection?
The sampling frequncy is normalise, if...
In Sigma delta DAC, what is the different between the 1 bit quantizer in the digital domain and the 1bit dac in the analog domain?
After the 1 bit quantizer , the output from the quantizer will be feed into the 1 bit DAC...does it use to shift the voltage level from digital domain to analog domain?
Thanks.. It works..
If i want to validate my system to get the same frequecy response. How should i do it?
Apply a signal and run transient...then how to plot the frequency response with the output data with matlab?
i have a transfer function H(z)=(1/m^2)((1-z^-m)/(1-z^-1))^2
In order to use the the command "freqz" i need to convert this transfer function to standard delay form..but i don't know how to convert due to the z^-m...
My m is 32...please help...thanks in advance.
I would like to design a cic filter as shown in the picture attach. The comb part is differentiator and the other part on the right is integrator. However i do not now how to implement the upsample (L).. I try to build it with simulink where the upsample(L) is a switch operate at higher sampling...
I would like to construct a cic filter for interpolation using simulink but not from the dsp toolbox. Figure shows the filter i have constructed. It does not seem to be correct..can someone help me out? Thanks
I would like to upsample 64 times, hence the switch is operate at the 64xfin...the...
my input sampling frequency is 41khz and would like to upsampling it to 82khz....so at the output (out@fs), should i implement a switch that switching at the frequency of 82khz for the upsampling purpose?
What do you mean by " what the interpolated samples should be placed between?
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