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Recent content by newcpu

  1. N

    Please refer book for memory design

    Are there any good books for memory ciruit design? And especially for memory decoder circuit design. Thanks a lot.
  2. N

    How to implement SRAM with standard logic (DFF)?

    How to design the decode logic for address? Thanks a lot.
  3. N

    What is Lock-up Latch?

    For DFT Compiler, lock up latch is inserted automatically if you turn on "-add_lockup true" for "set_scan_configuration".
  4. N

    RAM Implementation (standard cells method)

    Hi Lance850210, Could you share your verilog code example? Thanks.
  5. N

    How to implement SRAM with standard logic (DFF)?

    Are there any simple method to verify the verilog code for this? Thanks a lot.
  6. N

    How to implement SRAM with standard logic (DFF)?

    Hi, I want to replace those small SRAM/Register File compiled by memory compiler with standard logic (DFF). Could you help to provide some references? Thanks a lot. Best Regards, Newcpu
  7. N

    Is there any EDA tool for EMI for Mentor or Cadence

    Hi, Is there any EDA tool for EMI verification software at chip? Mentor or Cadence? Thanks a lot. Best Regards, newcpu
  8. N

    Are there any EDA tool for EMI verification software at chip

    Hi, Is there any EDA tool for EMI verification software at chip? Mentor or Cadence? Thanks a lot. Best Regards, newcpu
  9. N

    What is the effect of clock gating in design?

    Clock Gating Glitches can be avoid by using ICG cell in the library.
  10. N

    Which tool is better: Tetramax or Fastscan?

    fast scan tetramax Fastscan is better from the DFT itself. TetraMax is better from the tools' understanding to logic.
  11. N

    Could anyone provide any documents about .lib

    Could anyone provide any documents about how to understand the .lib provided by foundaries such as TSMC? Thanks a lot.
  12. N

    What should I prepare for the coverage estimation if I have insert scan chains?

    help me You can use command -- estimate_coverage in DFT compiler.
  13. N

    The difference between VHDL and Verilog.

    or_reduce vhdl The functions of them are almost the same. Verilog is more popular in USA while VHDL is more popular in Europe.
  14. N

    Help: timing loop and latch

    In order to avoid latch when coding with verilog, we add "else C<=C" as following: always @(posedge clk) begin if(A==1'b0) C<=B; else C<=C; end But for combinational logic, the...
  15. N

    synopsys designware PCI/PCI-X VIP

    Also for synthesis with their db or lib.
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