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Recent content by newbie123FPGA

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    Spartan 3E Digital Clock Manager Problem

    I am using a DCM to go from 50 MHz to 25 MHz.This code was just for confirmation and it doesn't work.I've listed 'clk' as output to view DCM output.It's exactly hal of input CLK, as it should be.When I change to @posedge CLK, the simulation works, with the DCM output clock, the always block...

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