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Recent content by nesta

  1. N

    sending messages in uart from fpga

    Hi VhdlExperts, I have implemented a design in simulator and it works perfectly fine, however when i synthesize in fpga i dont see any output. So im not sure how to debug this black box. I have used the led method but its very difficult for me to read all outputs just with leds. so i have...
  2. N

    Source Navigator for vhdl project

    Hi VhdlExperts, Is there any good free source navigator for vhdl files. What navigators do you all use for big projects to browse through the code. Thanks
  3. N

    Dimensions of 2-d array

    eg: array2d[row][col] array2d'length will give me only the number of colums, but how to find the number of rows??
  4. N

    Dimensions of 2-d array

    Hi, How to find dimensions of a given 2-d array in vhdl? is there any standard attribute to find the dim. Thanks
  5. N

    For loop timing query

    Hi VhdlExperts, I would like to understand about how the timing is decided. For example if i have a for loop inside a process which runs on every rising edge of the clock signal, Is it guaranteed that the for loop will complete within one clock cycle. eg: test: process(clk) begin if(clk...
  6. N

    Signed fixed number - 2s complement

    Hi VhdlExperts, What is the algorithm to find a 2's complement for a signed fixed point number. I would like to implement this so would need the algorithm. eg: 2s complement of (-1.5). Thanks in Advance.
  7. N

    ISIM sfixed values looks wrong.

    Hi VhdlExperts, I am using Xilinx webpack 12.4 ISIM and see some strange results for sfixed values especially for negative numbers. for eg: signal Ain : sfixed(7 downto -3); Ain <= to_sfixed(-2.5),Ain); gives me 11111101100 (ie 11111101.100 ) instead of 11111110.100 ----- Ain <=...
  8. N

    How to check for invalid data

    Hi VhdlExperts, Is there a way to check if the vector is uninitialsed 'U' or unknown 'X' as i have a scenario where i need to check for only valid data. Basically I want to latch only valid data. ---- if(clk ='1' and clk'event) then if(input = 'U' or input = 'X') then -- just...
  9. N

    conversion of sfixed values

    Thanks TrickyDicky for such an excellent explanation, Its very useful. I was using the scalb function to do the conversion will that cause any issues. i dont mind truncating the fractional part though after processing. Ain <= scalb(Bin,2)
  10. N

    conversion of sfixed values

    Hi VhdlExperts, I am not finding ways to typecast/ at least convert between the following (fixed point values) sfixed values. Plz suggest. signal Ain : sfixed(3 downto -4); signal Bin : sfixed(7 downto -8 ); Ain <= to_sfixed(Bin,Ain) -- something like this. Thanks in advance, Nesta
  11. N

    Simple synchronisng problem.

    Hi VhdlExperts, I have very simple doubt on synchronising data. I have 2 logical blocks which outputs (8bit vector) for further processing at the next block-3; The data to the block-1 might come faster than the data to the block-2 and similarly either of them might output faster, so how do i...
  12. N

    generating a 1 clk cycle pulse

    Sorry for not being very clear, basically i am using this ready signal (as an asynchronous input) for some kind of data pattern assertion. I would like to assert the ready signal (~1clk cycle) only whenever there is some known data pattern; rest of the time it should be deasserted. data =...
  13. N

    generating a 1 clk cycle pulse

    Sorry couldn't quite understand how to assign the ready signal .. cud plz elaborate with some simple pseudocode.
  14. N

    generating a 1 clk cycle pulse

    Sorry for the mistake, the actual code is (rdy_con )which is connected to the input rdy,, It was just a barebone to explain my intentions. rdy_con <= '0'; --- this does not toggle to zero(why) J_andr thanks for your suggestion , will try out.
  15. N

    generating a 1 clk cycle pulse

    Hi VhdlExperts, i have a requirement in which i need to generate a ready pulse for 1 clk cycle on some condition. However i am not finding a way to do it with a process having sensitivity list in it. The scenario is the rdy signal will be set high by a different process and it should be only...
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