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I'm new to TimeQuest and have some confusion here:
When I use "set_max/min_delay" command for a particular path in SDC file, is it only used for analyzing the timing eg. simply telling me if that particular path has timing violation based on the specified value, or is the command used to guide...
To have a large external memory bandwidth, can I instantiate any number of external memory controllers as long as there is enough hardware resource?
Is external memory only connected to dedicated I/O pins in a FPGA? or any pins can be used by the memory controller to connect to an external memory?
I want to write to a DDR2 RAM from a custom architecture. The RAM has 64bits data width and runs at 400MHz. The custom architecture is interfering with the memory controller by using Avalon-MM interface. The memory controller is set to half-rate mode which means local data width is 256bits and...
Is there any way I can code an OR/AND gate more efficiently?
For instance:
wire in_1, in_2, in_3;
wire out_1, out_2;
assign out_1 = (in_1||in_2||in_3);
assign out_2 = (in_1&&in_2&&in_3);
Three inputs is fine for the above example, but what if I've got 500 inputs?
When I ran a testbench in modelsim I've got vsim-8630 error referring to a line: result = A/B + C/D;
A,B,C and D are 'real', A = 17396, B = 186, C/D=1, therefore the result does have an infinite result.
Although in modelsim this error was reported, correct result was shown in waveform with the...
This question does not involve any specific circuit design since it's just a general question in my mind regarding designing practice. But here's a revised question:
If signal a and b are registered outputs of the same combinatorial logic, one is positive triggered and the other one is negative...
Could you clarify this, why do you think 'a' is clearly from another clk domain? Isn't it also possible to get signal 'a' by delaying signal 'b' for half cycle (using FF triggered by falling edge of 'clk', is it correct?).
As I mentioned in the original post, both 'a' and 'b' are registered...
uh..sorry..30mins passed, I can't edit the original post, here's the figure. But since you easily figured out it's a homework question, it shouldn't be difficult for you to understand the question without the figure right :)?
Hello, I've got two questions about using ff triggered by falling edge of the clock:
1) As shown in the figure, if I use both signal a and b to drive the same circuit that is also synchronised to 'clk', is 'a' more stable than 'b'? (Here stable I mean glitch-free)
2) How should I analysis...
In "Memory List" tab in ModelSim, one can check the values of the entries in a RAM block directly through GUI, however is it possible to access these values in a testbench, where the values can be directly accessed and compared with some truth table without following the specific timing scheme...
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