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Recent content by neo_anderson

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    sroute blockring connectivity

    Thanks again for your remarks. I will try to put soon the LEF file. The thing that i cannot understand is, it works well for one of the POWER nets. Is there an option is sroute that I could allow the ring to extend outwards to connect to the followpins ?? The situation is now it trys or...
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    sroute blockring connectivity

    Thanks for your message. Yes the LEF file contains the pins vdd! and gnd! But I am not sure, whether it should also contain the "CLASS CORE" under PIN too. (which actually present under Macro definition) Here is a part of the LEF file of a macro PIN vdd! DIRECTION INOUT ; USE...
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    sroute blockring connectivity

    To add more to the previous question, Is there an option to make the Sroute to connect block pins/nets outward to a stripe or ring. The encounter is not able to place the vdd! net via because it might short the gnd!, so Is it possible extend the ring outside and connect to the respective...
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    sroute blockring connectivity

    Hi yes they are, net name gnd! and pin gnd!, same for the vdd! globalNetConnect performed. In addtion, I also get the following warning message with sroute: (sroute performed before placement) Begin power routing ... **WARN: (ENCSR-1253): Net vdd! does not have standard cells to be routed...
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    sroute blockring connectivity

    Hi, After addstripes, I run the sroute. I have a lot of memory blocks in my design around the corners. As i perform sroute, I see that my vdd! nets (the followpins) is not connected to the blockring but it managed to place via for the gnd! followpins. Similarly at the IO pads, the gnd! nets...
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    Error Launching ncvlog

    ncvlog 32 bit hi thanks,,, i guess i found the sollution. The problem was... All of the versions of IUS's Binary file was pointing to /64Bit directory. and i went through the /32bit directory... the files of ncvlog,nclaunch ... did not existed. I dont know why? i guess it is some...
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    Error Launching ncvlog

    ncvlog Hi all, I was trying to simulate a verilog-AMS, and make a symbol, but i occured error. (using version: ius_v5.7_qsr1) --------------------------- ncvlog(64): 05.70-s001: (c) Copyright 1995-2006 Cadence Design Systems, Inc. ncvlog: *E,AMSN64: Verilog-AMS not...
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    Suppressing warnngs and errors in modelsim simulation

    hi, Actually i am doing a repeated simulation, iteration for example 30 run.programed in java to do the iterations. and implemented in pipe. the Problem is that these warnings that pop up in simulation fills out the java buffers and the simulations stops. so thats the reason i need to...
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    Suppressing warnngs and errors in modelsim simulation

    hi, but i see these warnings come from the $display statements in the memory.v For temperory i did is just remove those $display statement. but i guess this is not the right way to do it. i want to remove these notes. thanks dinesh
  10. N

    Suppressing warnngs and errors in modelsim simulation

    Hi all, I want to suppress all warnings and errors in the simulation of modelsim. Especially the notes and warnings / errors that i get after initialization of memories. Thanks dinesh
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