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hi,
I amusing $fopenw and $fwrite for dealing with my filein my verilog code.
every time my code enters always@(posedge clk) block , i want to rewrite my file (not append to the end of the file),
in other words i want to clear my file and then write it again.
is there any way to clear a file...
Hi,
I want to know that is it possible to convert verilog or VHDL to other processor's assembly code(such as Intel) ??
is there any special converter??
tnx
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