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The testbench worked fine for my behavioral code, but I get the error when I try to use it for my structural gate-level netlist:
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--header file
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library IEEE;
use IEEE.std_logic_1164.all;
entity inv is
port(inb: in STD_logic;
outb: out...
I would really appreciate your help. I wrote the following testbench code to test my 6th order FIR filter. It worked perfectly for my behavioral code, but when I try to use it after synthesis for my structural gate-level netlist, I get this error:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE...
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