Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by nearers

  1. N

    VCS on the Ubuntu Linux

    Thanks dapul, In my case, even basic VCS is not working. I cannot execute any VCS command.
  2. N

    STARRC - Synopsys Error message

    Thanks rca, Sorry, it is still not clear for me. My current problem is "WARNING: File '.tmp_file' does not exist, sleeping for 30 sec. before checking again. (SX-3050) " this warining. Is the MAPPING_FILE related to this warning? I have checked my mapping file and it was from our...
  3. N

    VCS on the Ubuntu Linux

    Hello Everyone, I have installed Synopsys VCS tools on the ubuntu 14.04 LTS. Our lab usually used VCS tools on the other OS systems such as Fedora and CentOS without any problems with our University License. Could you please see this error messages and let me know the problems of my...
  4. N

    hercules nettran - System Verilog netlist file?

    Hi dpaul, I am design some specialize circuit. I cannot use normal Boolean standard cell library. I have no library but I just have schematics of my user-defined cells. The System-Verilog net-list file has the connectivity information of my cells. I would like to simulate this net-list using...
  5. N

    STARRC - Synopsys Error message

    Thanks rca, Yes, it is actually not an error message but finally the result was not successful. You mentioned this "well you need to fix the map file used to map the layers between the LEF/GDSand DEF files." but I could not clearly understand that. I am a newbie on this tools. Could you please...
  6. N

    hercules nettran - System Verilog netlist file?

    Hi I have a private net-list generation tool and it is generating System Verilog net-list. I would like to convert this System Verilog net-list to spice netlist for the analog simulation on the Ultrasim and Spectre. Does "hercules nettran" support System Verilog net-list input file? If not...
  7. N

    STARRC - Synopsys Error message

    I have executed StarRC using command mode but the log file generated these errors and repeated many times and finally the command was unsuccessful. The command generated extracted view properly but I want to know the details of these error messages.

Part and Inventory Search

Back
Top