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I guess that you implies the delay count?
If so, you should examine the polynomial order of the FIR/IIR filter.
For example, a filter usually can be expressed as the following form:
H(z) = A0 + A1 * z-1 + A2 * z-2 + ... + An * z-n
where Y(z) = X(z)H(z).
If n is finite, such as n = N...
Anna, Thanks for your reply,
Finally I minimized the oscillation by adding a RC damping circuit between Gate and Source.
Do you have any suggestion in layout? Can it be optimized if I coat the Ground among the path of the Bridge OUT ?
Thanks for reminding, I should update my schematic to avoid confusing.
In my realization, I didn't attach D5 and D6, avoid the reverse charge on the D5 and D6 to build caps.
Thank you for your reminding, sorry that I didn't update my schematic. In fact, I had it already.
I think your are mentioning the R29 resistor in my layout, which connect from the MOSFET output to the Vs in HVIC, for protecting the HVIC from being harmed by negative voltage.
Thanks for reply, I had connected the U6 com and Q4 source by soldering a wire, but it didn't help.
Is there anything I missed?
What if there is any problem in the +12V power for the HVIC and bootstrap cap to work?
- - - Updated - - -
D3 and D4 I used are MUR160 (Ultra Fast Diode, D3 is...
Dear All, thanks for your helping. Now I post the Vgs-Vds for High Side MOSFET and my layout of HVIC.
Vgs-Vds for High Side MOSFET:
The Vds looks well, but when I increase the VDD higher than 130V, the wave start the distort.
This is my layout of HVIC, D+ and D- are my differential PWM...
Dear all,
I designed a Half H bridge by a HVIC switching circuit, but I encountered some problems.
This is my schematic.
The circuit is working perfectly when I applied the VDD below 100V.
Following is the chart from oscilloscope, for the Vgs of both up-side and low-side MOSFET...
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