Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I am doing a project of designing ADPLL using cyclic vernier time to digital converter ,I have designed Time to digital converter and stuck with the design of Digital loop filter.
Can any body help me how to calculate coefficients for DLF.
and please provide me DLF code...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.