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Recent content by naveenkumarmadala

  1. N

    instantiation problem with sequential blocks in verilog

    thank you
  2. N

    instantiation problem with sequential blocks in verilog

    hi,here i am sending my testbench.please refer it once. module mnk_kr_tb; reg clk; reg rst; reg [7:0] in; wire [7:0] out; mnk_kr uut ( .clk(clk), .rst(rst), .in(in), .out(out) ); initial begin rst = 1; in = 8'b10100110; #100; rst = 0; in = 8'b10100110; end...
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    instantiation problem with sequential blocks in verilog

    i am sorry for that.my original idea is first i have to design a module(A) which has 8 bit input and 8 bit output.with such module(A) i want to generate another module(B) with 8 bit input and 8 bit output by instantiating 8 first module(A) provided output of each module is input to the next...
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    instantiation problem with sequential blocks in verilog

    hi, i am trying to write a verilog code to generate TPG's.while i simulating the code it is showing the error as "Instantiation is not allowed in sequential area except checker instantiation".here i am attaching my code.please give me suggestion to remove the error. module mnk(clk,rst,in,out)...
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