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Recent content by naveeneceng

  1. N

    [SOLVED] Doubt in Verilog module instantiation.. Help Me please....

    module MUL_FOUR(A,B,P); input [3:0]A; input [3:0]B; output [7:0]P; reg [3:0]s1,s2,s3,s4,s5; reg c1,c2,c3,s6; parameter zero=0; MUL_TWO M1((A.A[1:0]), (B.B[1:0]), P.s1[3:0]); MUL_TWO M2((A.A[3:2]), (B.B[1:0]), P.s2[3:0]); MUL_TWO M3((A.A[1:0]), (B.B[3:2]), P.s3[3:0])...
  2. N

    [SOLVED] Doubt in Verilog module instantiation.. Help Me please....

    I have a sub module module RCAF(a,b,s,cout); input [3:0] a,b; output [3:0] s; output cout; wire c1,c2,c3; here input a b are 4 input buses... if i want to instantiate the above module RCAF A1((a.s2),(b.s3), // here s2 nd s3 are 4 bit buses. (s.s5), (cout.c1)); Say if i want...
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