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Recent content by naughtyboy

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    how to AC simulate an OTA with switched-cap CMFB?

    Howdy- I'm currently designing an OTA for sigma-delta modulators. When continuous-time cmfb is utilized, all the simulations show good results. However, when I change to switched-cap cmfb, trans simulations are okay, but how to simulation the AC response? Any hints?
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    Is a SAW filter is an active filter?

    passive, may costs 2dBm power loss.
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    Direct conversion becomes a common practice for CMOS radio

    Re: Direct conversion becomes a common practice for CMOS rad Wide bandwidth and spread-spectrum technique make it possible to employ direct downconversion receivers. The negative effect of DC offset and flicker noise is reduced to a negligiable level. IEEE802.11a is very suitalbe for dir-con...
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    How the MOSFET threshold voltage varies with corner cases?

    Re: corner analysis of Vth I use ADS2003, so you can get the device info my "detailed device ...". If you use HSpice, there is a commond to extract the DC parameters and put in the *.lis file. Usually the input signal bias is not decided by the Vdsat of a current mirror underneath, but it does...
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    superhetrodyne transceiver

    Superhetrodyne receiver translates the RF to so-called IF by the first mixer to perform filtering and amplification. So the filter at RF and IF is refered to as Channel select filter and Image reject filter, which bring good performance. Then, the IF signal is downconverted to the baseband by...
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    Using Tanner Tools for Analog IC design

    Tanner is a good package for small scale and analog IC design. It supports full customer design methodology, like: schematic->spice simulation->layout. T-Spice and Ledit are all good, but never rely on the place and router. The potential problem for a complicated design are: 1) Doesn't have the...
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    How the MOSFET threshold voltage varies with corner cases?

    Re: corner analysis of Vth Vth is also related to the channel DC bias. MOSIS only supports N-Well, so for a NMOSFET, the channel is always tired to ground. So the threshold voltage may be a lot higher than Vth0, when the source is not grounded.
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    how to get cut-off frequency waveform from Cadence

    I remember that I did that using AC simulation. Plot the gate current Ig and channel current Ids to evaluate the omega_T.
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    cadence techfile to laker conversion

    Hi, anybody knows that there is a way to convert the cadence layout techfile to laker ?
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    Noise figure in ic5033 (sp simulation)

    noise figure in ic5033 When using ic5033 to do sp simulation, it looks that there is 0.4-0.5 dB noise figure loss compare to ic50 on the same LNA circuitry. Anybody has got some idea about "what's new" in ic5033? BTW, the display and simulation speed improved a lot in ic5033.
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    what is the difference between Diva and Dracula in ic5?

    what is the difference between Diva and Dracula in ic5? They look all do DRC and ERC, then why need two? Have a good day!
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    ic5 display very slow when using 24bits color

    Just upgraded XFree86 to Ver 4.1.50. It does help a lot on ic5. The display is now much faster.
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    ic5 display very slow when using 24bits color

    On my RH7.2 linux box, ic5 Linux version has serious display problem when using 24 bits color. It occupies too much CPU resources when operating the wave window or layout window. Anybody encounted the same problem? I'm just wondering that if update Xfree86 to Version 4 would help or not?
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    Is c@dence Design_pl@nner included in !c5?

    Is c@dence Design_pl@nner included in !c5? If is not, how you guys do place and routing using !c5?
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    Is Tanner Ledit auto router suitable for big designs?

    Tanner auto router Anybody tried Tanner Ledit before? How is the place and router for a 100k chip? Thanks

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