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thanks volker and sunnyskyguy.
@volker, nope i am not looking for a diplexer.
@sunnyskyguy, i roughly get what you're pointing at. However, I am doing an on chip design using 65nm cmos process. FET will be a good candidate to implement the switches but it isn't as easy as using a voltage...
Hi gurus,
I would like to create a switch that is dependent on specific input frequencies ie
4 switches and 2 paths. Depending on frequency.
f1 (say 2GHz) - turn on only switch 1 and connect both the input and output
f2 (say 3GHz) - turn on only switch 2 and connect both the input and output...
Hi everyone,
I have designed a simple QPSK transmitter to test the ACPR and EVM of my PA.
However, I have some trouble with the component VtLFSR_DT in ads. (**broken link removed**)
Apparently the taps and seed will affect my results and I am still lost after looking at the guide as I am an...
Hi All,
Sorry i have some questions pertaining to the OFDM transmitter block in ADS again.
I am running for 60GHz and have changed the parameters accordingly. I have also changed the RF PA to that of mine because I want to check the ACPR results of the RF PA that I have designed.
However...
ofdm simulation of PA for ads
Hi guys,
I have currently a 60 GHz PA block that i would like to run an ACPR and EVM simulation to check its linearity. IMD3 and IIP3 have been ran.
Would like to do it in the ADS environment but looking at the OFDM transmitter design guide, i have no idea how to...
Hi johnjoe,
You're right. My input signal should range between -20dBm to 10dBm typically, base on the IEEE standard and research standard for 60GHz. And yes, there's a harmonic filter. So small input signal could result in the deviation?
Natnoraa
- - - Updated - - -
Hi johnjoe,
It's okay...
Hi johnjoe,
Alright I'll look into this first. I've seen too many documents on load-line and output signal = input signal. The example if i were to increase Vg to 1.4V I will be getting it but still why it's << 2.5V that's the question. Thanks for now.
Natnoraa
Hi johnjoe,
I understand your point. Yes it's an ideal inductor still so there's 0 ohmic loss. However, my question is as per my first post. According to theory, half point towards max Ids will be my class A biasing point ie. 2.5V Vg. However, at 1.1V (or safely assume 1.2V) I'm already getting...
Hi johnjoe,
Thanks for your reply. By meaning of simulating with VCC/2, i suppose it's simulating Vdd to be 0.6V and everything else the same. Here is the waveform:
P.S: What's the purpose of reducing the VCC by 2 here?
Natnoraa
Hi everyone,
Am questioning the reason behind these discrepancies and have yet to convince myself so here it is:
Linear amplifiers are classified as such according to theory:
I ran a PDK transistor and this is what I'm getting:
Question: Looking at what I'm getting, shouldn't a Class A...
1) Solved. I must go back to HFSS and found that port 3 is actually the transmitted port looking at the phase S31. it leads S21 by about 90 degree and thus port 2 should be the coupled port. By connecting port 1,3 and 2,4 one can get the correct differential results
2) Solved.
3) Solved. Got a...
Hi,
I have designed a multi-layer quadrature hybrid coupler(can be offset) in HFSS and assigned 4 ports to it as shown:
Port 1: input
Port 2: transmitted
Port 3: coupled
Port 4: isolated
Step 1: I designed each layer to be a quarter wavelength at the frequency of my interest. Such that...
Hi,
I am sure you have matched your input wrongly (assuming you're tackling the problem of your S11 now). Make sure you conjugate match the input impedance.
Natnoraa
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