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HI,
Currently I am designing V to I buffer. As current was the o/p it was giving, how we can measure effect of supply noise on current output.
Another question is how we can simulate output noise current for the same circuit.
Thanks
N.koteswararao
Hi all,
In my schematic there is transistor MP3 at hierarchy DCDCDAC_0/dac_sl/I43 level.
To plot operating point drain current in this transistor I am using expression OP("/DCDCDAC_0/dac_sl/I43/MP3","ids").
Till now it was fine.
For post layout(extraction) simulation there was no hierarcy...
1) I had designed ring oscillator with 3-stage differential amplifier with resister load. when bias current for differential stage in constant, I observed frequency is changing with temperature. But with PTAT current frequency is constant with tempearture. I didn't undersatnd what was the...
I am doing corner simulation using spectre decks in 40nm technology.
To change process I am using altergroup statement as below:
alter2 altergroup{
include "modelfile"
}
Now it was showing error:
ERROR (SFE-700):
"modelfile"
3214: altergroup statements cannot be specified within...
As i mentioned vsense and vdd_1v1 are shorted in actual case. This node is low impedance node because of pmos common gate.
It is not giving correct phase response as well as dc loop gain also.
What value of gain margin is required for smooth transient response? why?
there may be systems with good PM as 60degress, and bad GM as 3dB(because of RHZ after UGB.
I had doubt regarding Gain Margin.
I know importance of Phase and Gain Margin those values make sure loop stable.
To have transient response smooth without ringing, we require phase margin of 60degrees.
What value of gain margin is required for smooth transient response/
I saw many literature...
In the attached circuit is driving capacitance load and current of 5mA.
sense and vdd_1v8 pins are shorted outside.
To check stability and see loop gain and phase response for this circuit, where exactly i need to break loop?
I am designing self biasing current source, I need to provide extra pin bias_ok such that Bias_OK should go if HIGH the final current is in the range of +/-10 of its final value. Can someone pls share idea how to add this pin.
My current is settling in 200us with some ringing and startup is off...
I want to simulate using spectre, using PSS+PAC(if possible)/other analysis.
I don't know what inputs to specify for simulator to check filter frequency response
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