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Level shifter and Isolation should never be powered off. For V1, there should be two domains, V1ON, and V1OFF, and the same for V2. So it is something like
V1OFF->Isolation(V1ON)->LevelShifter(V1ON/V2ON)->V2OFF
Nandy
NanDigits Design Automation
You can create another AHB address for empty signal polling. So FIFO data write uses one AHB address(Or maybe a serial of addresses), polling EMPTY signal uses another AHB address.
V1-> Level Shifter -> Isolation->V2 would violate power rule. When V1 is off, Level Shifter has cell driven by power down block directly.
If V2 can be powered off as well, then V2->Isolation->Level Shifter->V1
Comparing with reset flipflops, non-reset flipflops are smaller and less power consuming. Normally, datapath uses non-reset flops. State machines flops use reset flops. One good thing to use all reset flops in a design is you have less trouble to trace 'x' propagation issue in gate level simulation.
Thanks for pointing out. Actually for timing ECO case, it's enough to compare D pins. In full function comparing mode, two flop instances should be selected and compared. Check the image for flop to flop equivalence check.
This is a real case. A timing ECO iteration added an extra inverter somewhere in the design. Hundreds of inverters/buffers have been added, it's impossible to check one by one to see which inverter is the extra one. Debugging with Formal tools shows lots of support points causing the mismatches...
Hi ivb1991, Gates On the Fly can handle your case. The patches keep the library cells from revised netlist (reference netlist in GOF)
You can use this script example
# eco.pl
read_library("art.90nm.lib");
read_design("-ref", "reference.gv"); # Resynthesized netlist
read_design("-imp"...
The simplest script would be:
read_library("art.90nm.lib");
read_design("-ref", "reference.gv");
read_design("-imp", "implementation.gv");
fix_modules("mod1", "mod2"); # all modules that have been modified
set_top("topmod");
write_verilog("eco_verilog.v");
Please check this link for...
Gates On the Fly from NanDigits has a new release to do automatic functional ECO. You only need input netlist under ECO and reference netlist, and tell the tool which modules have been changed. The tool will figure out the minimum gate patch to fix the netlist under ECO. It's fast and efficient.
You may have 'x' propagation in gate level simulation. You can use a initialization code to suppress 'x' generation.
Check this out.
https://www.nandigits.com/use_case_remove_x_in_gate_simulation.htm
Netlist ECO tool Gates On the Fly can do the job easily. You can use perl compatible script like following to add an AND gate to each D pin of each flop.
my @ffs = get_cells("-type", "ff", "-hier"); # Get all flops
foreach my $ff (@ffs){
my @dpins = get_pins("-input", "-data", $ff)...
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